Integrated circuits usually include circuitry and multiple logic blocks that may be configured to perform any of a variety of functions. Programmable integrated circuit devices such as field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., may include logic blocks or elements that can be configured to perform desired functions based on different user designs.
Apart from internal logic blocks that may be used to implement or perform different user functions, a programmable logic device generally includes input-output blocks or high-speed transceiver channel blocks that may be used to communicate with other components coupled to the programmable logic device through various input-output protocols.
As an example, the programmable logic device and any external components coupled to it may be part of a passive optical network (PON) structure. In general, a PON structure is a point-to-multipoint network architecture that allows a single provider node, commonly known as an optical line terminal (OLT), to serve multiple user nodes, commonly known as optical network terminals (ONUs). As such, the programmable device may be configured to implement a high speed communication protocol such as a Gigabit Passive Optical Network (GPON) protocol to communicate with any of the external components coupled to it.
However, several limitations need to be addressed when implementing a high speed communication protocol, such as the GPON protocol, in a programmable logic device. Some of the common challenges when implementing high speed communication protocols include, among others, long dead time, multiple phase shifts, and short recovery time. These problems arise partly because a clock data recovery circuit is generally used to recover a clock signal from an incoming data stream and the clock data recovery circuit in the programmable device may not be able to lock to the incoming clock signal within a relatively short period of time.
Incoming data may be lost if the clock data recovery circuit is not able to lock to the incoming clock signal within a single data frame. Moreover, different components or devices coupled to the programmable device may send data to the programmable device at different phases even though they may all operate at the same frequency. Therefore, information may be lost as incoming data may not be accurately sampled by the device.